The Semiconductor Industry Needs Continuous Improved Faults Coverage While Reducing The Overall Cost Of Test
Faults coverage is becoming more problematic as systems are getting more complex, heterogeneous and applications are more demanding. Applications such as self-driving cars, cloud servers, AI, industrial IOT or medical devices are now mission critical, driving the need for low parts per billion (PPB) defect levels.
Semiconductors continue to follow Moore’s law doubling the number of transistors at every process node. As these new process nodes come to market, higher numbers of smaller transistors will make it more difficult to catch defects, and will make test coverage more demanding.
Test coverage of 99.4% still leaves 15 million transistors untested on a 2.5 billion transistor device.
Time to market and time to revenue drives the need for shorter cycle time with increased faults coverage.
System level test in the customer application environment provides the ability to solve these challenges while providing an opportunity to significantly reduce overall cost of test.
A New System Level Test Solution (AMPS)
AEM Singapore has developed a new system level test solution (AMPS) that leverages the knowledge and experience gained over the last decade in system level device handling for leading semiconductor companies.
AMPS stands for Asynchronous, Modular Parallel and Smart as key parameters for system level testing.
System Level testers need to be modular and be easily customized and reconfigured as required for specific device applications. Working with customers to integrate their modified application evaluation module into a system test handling solution leverages the existing test development.
Providing a modular approach that can be replicated and scaled enables the same system to be used in engineering debug environments and ramped in production. The production solution needs to be completely asynchronous in operation to enable each system evaluation board to be completely stand-alone in operation. This facilitates the ability to reconfigure systems without taking a line down and enables individual smart device test flows.
Modularity by re-using the same modules enables scalability for massively parallel test handlers reducing the overall cost of ownership.
System is scalable from individual devices for engineering debug up to 480 parallel sites.
Optional individual device ATC thermal control from -40C up to 150C enables burn-in and stress test within the same system.
Adding optional system level functional test capability (SLT+) enables BIST, MBIST and functional testing within the same system. This provides the ability to configure a system for multiple different devices or modules to be tested at the same time supporting applications with a higher mix of products such as OSAT’s.
AMPS (Asynchronous, Modular, Parallel, Smart) System Level Test Enables Smart Knowledge Based Testing (KBT)
Traditional test flows include wafer test and functional ATE test.
Collecting system level test data enables correlation back to the functional test and wafer test results. Stored data and big data analytics enable smart knowledge based adaptive test decisions to be made between wafer, functional and system level test (SLT) further reducing the overall cost of test.
Adding optional functional test modules into the system level tester further enables adaptive test within the same system.
Advances in data analytics, machine learning and massive parallel test handling systems now enables a shift in test paradigm. System level testing is not a new concept but is now proven and ready to help increase faults coverage while reducing the overall cost of test.
ABOUT THE AUTHOR
Stuart Pearce, AEM Holdings
Contact information: firstname.lastname@example.org