In this insightful presentation, Stuart Pearce, Senior Director of ATE and Test Instrumentation at AEM, discusses the critical role of System Level Test (SLT) in ensuring the reliability of mission-critical applications using the latest Silicon process nodes at the Test Club Meeting by Tessolve.

Learn how advanced testing methods enhance fault coverage, with a focus on the need for massively parallel test solutions due to increasing test times. Gain valuable insights into testing in real-world applications, addressing system-level aspects such as closed-loop power and thermal management.

Watch the full video to explore the latest strategies and techniques for maximizing test efficiency and coverage in Silicon manufacturing.

For more information on the Tessolve Test Club, visit https://www.tessolve.com/introduction-to-system-level-test